1. Field of the Invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells with page erase and negative voltage gate erase. More particularly, the present invention relates to a distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure.
2. Description of the Prior Art
In and commonly assigned U.S. application Ser. No. 07/964,807 to M. A. Van Buskirk et al. entitled "Negative Power Supply" and filed on Oct. 22, 1992, now U.S. Pat. No. 5,282,170, there is described a negative power supply for generating and supplying a regulated potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure. This application Ser. No. 07/964,807 is hereby incorporated by reference in its entirety. In FIG. 1 of the '807 application, there is shown a block diagram of the negative power supply 10 which includes a clock circuit 14 for generating a plurality of clock signals and a charge pumping circuit 12 responsive to an external power supply potential VCC and to the clock signals for generating a high negative voltage. A cancellation circuit is coupled to the charge pumping circuit for effectively canceling out threshold voltage drops therein.
The charge pumping circuit 12 of the '807 application is formed of a plurality of charge pumping stages. A negative well circuit 20 is coupled to the plurality of charge pumping stages for preventing initially the operation of a certain number of the plurality of charge pumping stages during erasure. A regulator circuit 16 is responsive to the high negative voltage and a reference potential for generating a negative comparator signal which is either at a high level so as to allow the charge pumping circuit to increase the high negative voltage or at a low level so as to decrease the high negative voltage and for generating the regulated negative potential that is independent of the power supply potential VCC.
The charge pumping circuit 12 and the negative well circuit 20 represents only one of the sixteen charge pumping circuits used on the integrated circuit chip containing the array of flash EEPROM memory cells. Each one of the charge pumping circuits is associated with one of the eight half-sectors in either the left or right side of the array. Further, the high negative voltage NEGOUT from each of the pumping circuits is coupled to the wordlines via a plurality of diode-connected P-channel transistors P9 as shown in FIG. 4(c) of the '807 application. One of the disadvantages in this prior art negative power supply utilizing 16 charge pumping circuits is that a large amount of space is required on the integrated circuit chip. Further, there are accompanying drawbacks of high power consumption and high heat dissipation. In addition, there exists another drawback due to the diode connected transistor causing a voltage drop V.sub.t dependency of the wordline voltage during erase.
The present invention represents a significant improvement over the prior art negative power supply discussed above in the '807 application. The distributed negative gate power supply of the present invention is used for generating and selectively supplying a relative high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The distributed negative gate power supply includes a main charge pumping circuit for generating a relatively high primary negative voltage and a plurality of distribution sector pump circuits, each corresponding to one of the half-sectors. The distribution sector pump circuit is used to selectively connect the primary negative voltage to the wordlines of the selected half-sectors.